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Rev	Log message	Author	Age	Path
92	Update!	mihad	7720d 13h	/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7756d 03h	/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7756d 03h	/
89	Burst 2 error fixed.	mihad	7792d 03h	/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7798d 02h	/
87	Updated acording to RTL changes.	mihad	7810d 00h	/
86	Entered the option to disable no response counter in wb master.	mihad	7810d 00h	/
85	Changed Vendor ID defines.	mihad	7810d 04h	/
84	Changed vendor ID.	mihad	7813d 23h	/
83	Cleaned up the code. No functional changes.	mihad	7838d 21h	/
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7852d 17h	/
81	Updated synchronization in top level fifo modules.	mihad	7852d 17h	/
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7855d 22h	/
79	Updated.	mihad	7855d 22h	/
78	Old files with wrong names removed.	mihad	7855d 23h	/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7855d 23h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7858d 22h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7861d 23h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7861d 23h	/
73	Bug fixes, testcases added.	mihad	7861d 23h	/
72	* empty log message *	mihad	7909d 03h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7916d 19h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7954d 02h	/
69	Changed BIST signal names etc..	mihad	7954d 02h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7957d 12h	/
67	Changed BIST signals for RAMs.	tadejm	7957d 17h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7961d 03h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7964d 01h	/
64	The testcase I just added in previous revision repaired	mihad	7964d 03h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7964d 05h	/

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