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Rev	Log message	Author	Age	Path
47	Tag version 0.1 of the Potato Processor	skordal	3307d 13h	/
46	Remove branch: cache-playground	skordal	3310d 07h	/
45	Merge branch cache-playground (r23-r30 and r34-r44) into trunk This primarily adds the following features the the processor: - A direct-mapped instruction cache with configurable cache line width and number of cache lines. - Various bug fixes for bugs that appeared when the processor could run instructions at full speed but had to stall for data. - A "Hello World" test application.	skordal	3310d 07h	/
44	Add instruction cache and use the WB adapter as dmem interface	skordal	3310d 07h	/
43	Improve instruction fetch logic	skordal	3310d 07h	/
42	Move check for stall from irq_asserted to exception_taken in EX stage	skordal	3310d 07h	/
41	Make continouous status register reads asynchronous	skordal	3310d 07h	/
40	Reduce example design clock frequency to 50 MHz - Also includes a minor change to make the address decoder/interconnect work better with burst transfers.	skordal	3310d 07h	/
39	Disable IRQs when handling exceptions	skordal	3310d 07h	/
38	Add "Hello World" test application	skordal	3310d 08h	/
37	Add macro to set the TOHOST register from C code	skordal	3310d 08h	/
36	Ensure correct read of CSR after stall	skordal	3310d 08h	/
35	Prevent jumping/branching when stalling	skordal	3310d 08h	/
34	Prevent flushing the pipeline if it is stalling	skordal	3310d 08h	/
33	Ensure correct read of CSR after stall	skordal	3310d 09h	/
32	Prevent jumping/branching when stalling	skordal	3313d 06h	/
31	Prevent flushing the pipeline if it is stalling	skordal	3313d 07h	/
30	Add testcase for a combination of instructions that fail when using cache	skordal	3315d 11h	/
29	Add reset functionality for the WB arbiter state machine	skordal	3318d 06h	/
28	Add rudimentary User's manual	skordal	3324d 06h	/
27	Prevent exceptions from being taken while stalling	skordal	3324d 08h	/
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3324d 11h	/
25	Add placeholder cache modules and a wishbone arbiter	skordal	3326d 15h	/
24	Remove unused STRINGIFY macros	skordal	3327d 04h	/
23	Create branch to use for implementing a cache	skordal	3327d 04h	/
22	Fix the potato_get_badvaddr() macro	skordal	3327d 05h	/
21	Upgrade the example design to use a 60 MHz system clock	skordal	3327d 05h	/
20	Fix SHA256 benchmark crash by storing all registers on exception handler entry This problem will disappear when the processor is updated to conform to the new supervisor specification, which will allow us to use a compiler that conforms to the new "official" ABI.	skordal	3327d 05h	/
19	SHA256 benchmark: allow compiler to inline at will	skordal	3327d 05h	/
18	instr_misalign_check: add do_jump to sensitivity list	skordal	3329d 05h	/

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