Rev |
Log message |
Author |
Age |
Path |
213 |
Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) |
jguarin2002 |
4353d 17h |
/ |
212 |
DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. |
jguarin2002 |
4353d 17h |
/ |
211 |
Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! |
jguarin2002 |
4353d 17h |
/ |
210 |
Document advance..... towards dma oriented raytrac |
jguarin2002 |
4365d 06h |
/ |
209 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
208 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
207 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
206 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
205 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
204 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
203 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
202 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4365d 06h |
/ |
201 |
files no longer needed im.vhd and fadd32long.vhd |
jguarin2002 |
4365d 06h |
/ |
200 |
raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers |
jguarin2002 |
4365d 06h |
/ |
199 |
Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work |
jguarin2002 |
4381d 12h |
/ |
198 |
Check out for the best out for the best organization so the datapath does not consume to many logic cells |
jguarin2002 |
4381d 12h |
/ |
197 |
Chnages on interconnectivity: Check out the SGDMA Sheets |
jguarin2002 |
4391d 13h |
/ |
196 |
raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues |
jguarin2002 |
4395d 00h |
/ |
195 |
Document advance and changes in the design |
jguarin2002 |
4397d 21h |
/ |
194 |
Work In Progress |
jguarin2002 |
4413d 03h |
/ |
193 |
WIP: Main Document |
jguarin2002 |
4414d 00h |
/ |
192 |
Some change I dont realize what is it in the design document (xls) |
jguarin2002 |
4414d 12h |
/ |
191 |
Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. |
jguarin2002 |
4414d 12h |
/ |
190 |
M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... |
jguarin2002 |
4418d 20h |
/ |
189 |
Limiting Block size on the operands register to a maximum of 256 |
jguarin2002 |
4419d 02h |
/ |
188 |
Fitting Report |
jguarin2002 |
4420d 10h |
/ |
187 |
Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq |
jguarin2002 |
4420d 10h |
/ |
186 |
Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq |
jguarin2002 |
4420d 10h |
/ |
185 |
Well mulblock was a void inside file.... |
jguarin2002 |
4420d 23h |
/ |
184 |
Se quitó la palabra capítulo de los titulos de los capítulos. |
jguarin2002 |
4421d 03h |
/ |