URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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Rev	Log message	Author	Age	Path
50	There's now a descent testbench\!\!\!	jguarin2002	4872d 04h	/
49	Test bench ifs finally running	jguarin2002	4872d 23h	/
48	Developing first testbench.... also learning how to do it	jguarin2002	4874d 19h	/
47	Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation	jguarin2002	4876d 07h	/
46	simplified memory path	jguarin2002	4876d 10h	/
45	Magic is already written... now we shall set the testbench on fire\!	jguarin2002	4877d 22h	/
44	All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif...	jguarin2002	4878d 23h	/
43	Nothing to say, just working on the Test Bench...	jguarin2002	4879d 07h	/
42	no comment no tb yet:	jguarin2002	4880d 00h	/
41	Ram for the massses\!\!\!	jguarin2002	4882d 11h	/
40	test bench changes.....	jguarin2002	4882d 11h	/
39	Perhaps its a good idea to have a todo.txt file under version control	jguarin2002	4884d 08h	/
38	Tb ggodies	jguarin2002	4885d 23h	/
37	Testbenchgoodies	jguarin2002	4885d 23h	/
36	testbench for rtengine test	jguarin2002	4886d 10h	/
35	oops stderr -> stdout, fixed	jguarin2002	4886d 10h	/
34	No need for .h	jguarin2002	4886d 12h	/
33	Program to create a MIF (memory initialization file) in order to simulate RtEngine	jguarin2002	4889d 22h	/
32	carry_logic parameter added to uf entity	jguarin2002	4892d 13h	/
31	enable signal retaken, and error corrected, a really big mistake	jguarin2002	4892d 22h	/
30	enable signal retaken... ooops a little lapsus	jguarin2002	4892d 22h	/
29	enable signal dropped...	jguarin2002	4892d 22h	/
28	fix fow q10 on stage0 to stage1 opcode signal... i was not sure if the thing was the right thing.	jguarin2002	4892d 22h	/
27	Optimized code, using IEEE libraries and extra parameters to make a more legible code	jguarin2002	4906d 20h	/
26	Corrections on opcoder	jguarin2002	4907d 00h	/
25	Support to variable width and the possibility to choose between behavioral description and structural description	jguarin2002	4907d 01h	/
24	Added a more simple mux to opcoder implementation.	jguarin2002	4913d 17h	/
23	Doxygen documentation related changes.....	jguarin2002	4913d 18h	/
22	Doxygen Documentation related changes.	jguarin2002	4914d 09h	/
21	Doxygen documentation related changes.....	jguarin2002	4915d 00h	/

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