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Rev Log message Author Age Path
25 Correcting compiler errors in TestRioPcsUart.vhd magro732 3755d 05h /
24 Changing errornous use statement. magro732 3755d 05h /
23 Tagging alpha release 2.0.0. magro732 3871d 23h /
22 Tagging release 1.0.0. magro732 3871d 23h /
21 Branching of a single symbol version of the new RioSerial. magro732 3871d 23h /
20 Adding software C-stack and matching VHDL modules. magro732 3937d 01h /
19 Removing synthesis warnings. magro732 3962d 01h /
18 Making RioSerial entity the same as before+minor fixes. magro732 3963d 00h /
17 Removing latch and improving timing. magro732 3964d 00h /
16 Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing. magro732 3964d 01h /
15 All testcases are ok. Still needs some tweeks though. magro732 3968d 02h /
14 Most issues solved, testbench issues remains. magro732 3971d 01h /
13 Timeouts are working. magro732 3974d 01h /
12 Backup of recent work, debugging new RioSerial. magro732 3985d 00h /
11 Receiver ready, transmitter is compiling. magro732 3985d 01h /
10 Branch to develop support for parallel symbols. magro732 3985d 01h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4026d 13h /
8 Adding signal descriptions in comments. magro732 4070d 02h /
7 Adding missing generic parameters to RioPacketBuffer. magro732 4157d 06h /
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4157d 08h /
5 Uploading primitive documentation. magro732 4164d 00h /
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4186d 13h /
3 Adding RioPacketBuffer and testbench. magro732 4187d 05h /
2 Adding RioSwitch and testbench. magro732 4187d 07h /
1 The project and the structure was created root 4188d 13h /

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