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Rev Log message Author Age Path
116 writes to uart when write to reg 0 trinklhar 6415d 09h /
115 *** empty log message *** trinklhar 6416d 00h /
114 Uart 0.3 trinklhar 6417d 04h /
113 Uart reset funkt trinklhar 6417d 05h /
112 Uart drin aber signale nicht eingebunden trinklhar 6417d 06h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6419d 22h /
110 - Added missing file to CVS. cwalter 6420d 05h /
109 - Assembler code for ST produced wrong instruction format. cwalter 6420d 20h /
108 no message cwalter 6420d 20h /
107 - Added new example for memory testing. cwalter 6420d 21h /
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6420d 21h /
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6420d 21h /
104 - Added missing signal dmem_data_in. cwalter 6420d 21h /
103 - Added simulation for memory to behavioral.
- Added empty mif file for memory.		 cwalter 6420d 21h /
102 changed data pitch ustadler 6423d 02h /
101 - Signals for memory block where not always set. This resulted in a latch. cwalter 6423d 03h /
100 - Signal clear_in was missing in sensitivity list. cwalter 6423d 03h /
99 - Fixed problem with barrel shifter input signals where a latch has been
synthesized.		 cwalter 6423d 03h /
98 - Applied indenting tool. cwalter 6423d 03h /
97 Fixed bug: only set branch and clear signals if branch is actually executed. jlechner 6423d 04h /
96 - SR register is now computed in ALU stage. cwalter 6423d 04h /
95 - Write back now only updates SR in case of a LOAD. cwalter 6423d 04h /
94 Added signal from ex stage to register lock unit for clearing all register locks
when a branch is executed.		 jlechner 6423d 04h /
93 Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result. jlechner 6423d 04h /
92 Added logic for inserting a nop instruction when the pipeline is cleared. jlechner 6423d 04h /
91 - Computed new SR values from ALU result. cwalter 6423d 05h /
90 Added output signal for clearing all register locks when a branch instruction is executed.
This is necessary because the id stage could have locked registers for an instruction
that is cleared out of the pipeline due to the branch.		 jlechner 6423d 05h /
89 Added input signal for clearing all register locks. jlechner 6423d 05h /
88 - Added new patch for assembler. cwalter 6423d 05h /
87 no message cwalter 6423d 05h /

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