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Rev Log message Author Age Path
133 - Fixed bug with ST opcodes. cwalter 6362d 00h /
132 Added test program for testing uart. jlechner 6362d 00h /
131 Changed high active resets to low active ones. jlechner 6362d 00h /
130 Removed obsolete line jlechner 6362d 00h /
129 Sample assembler program for accessing uart jlechner 6362d 00h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6362d 00h /
127 Changed high active resets to low active ones. jlechner 6362d 01h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6362d 07h /
125 Fixed vhdl bugs trinklhar 6362d 07h /
124 Assigned UART signals to ports on top-level entity trinklhar 6362d 07h /
123 Removed UART again trinklhar 6362d 08h /
122 Removed UART again again trinklhar 6362d 08h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6362d 08h /
120 Added UART module to memory entity trinklhar 6362d 08h /
119 Uart wieder ausgebaut trinklhar 6363d 03h /
118 insert Uart address constant trinklhar 6363d 03h /
117 Uart im mem_stage trinklhar 6363d 03h /
116 writes to uart when write to reg 0 trinklhar 6364d 09h /
115 *** empty log message *** trinklhar 6364d 23h /
114 Uart 0.3 trinklhar 6366d 04h /
113 Uart reset funkt trinklhar 6366d 04h /
112 Uart drin aber signale nicht eingebunden trinklhar 6366d 06h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6368d 22h /
110 - Added missing file to CVS. cwalter 6369d 05h /
109 - Assembler code for ST produced wrong instruction format. cwalter 6369d 20h /
108 no message cwalter 6369d 20h /
107 - Added new example for memory testing. cwalter 6369d 20h /
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6369d 20h /
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6369d 20h /
104 - Added missing signal dmem_data_in. cwalter 6369d 21h /

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