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Rev Log message Author Age Path
134 Added second test program for testing uart. jlechner 6364d 14h /
133 - Fixed bug with ST opcodes. cwalter 6364d 15h /
132 Added test program for testing uart. jlechner 6364d 16h /
131 Changed high active resets to low active ones. jlechner 6364d 16h /
130 Removed obsolete line jlechner 6364d 16h /
129 Sample assembler program for accessing uart jlechner 6364d 16h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6364d 16h /
127 Changed high active resets to low active ones. jlechner 6364d 16h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6364d 22h /
125 Fixed vhdl bugs trinklhar 6364d 22h /
124 Assigned UART signals to ports on top-level entity trinklhar 6364d 23h /
123 Removed UART again trinklhar 6364d 23h /
122 Removed UART again again trinklhar 6365d 00h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6365d 00h /
120 Added UART module to memory entity trinklhar 6365d 00h /
119 Uart wieder ausgebaut trinklhar 6365d 19h /
118 insert Uart address constant trinklhar 6365d 19h /
117 Uart im mem_stage trinklhar 6365d 19h /
116 writes to uart when write to reg 0 trinklhar 6367d 01h /
115 *** empty log message *** trinklhar 6367d 15h /
114 Uart 0.3 trinklhar 6368d 19h /
113 Uart reset funkt trinklhar 6368d 20h /
112 Uart drin aber signale nicht eingebunden trinklhar 6368d 22h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6371d 13h /
110 - Added missing file to CVS. cwalter 6371d 20h /
109 - Assembler code for ST produced wrong instruction format. cwalter 6372d 12h /
108 no message cwalter 6372d 12h /
107 - Added new example for memory testing. cwalter 6372d 12h /
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6372d 12h /
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6372d 12h /

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