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Rev Log message Author Age Path
138 - Fixed binary to VHDL converter. cwalter 6400d 12h /
137 - Added binary to VHDL converter. cwalter 6400d 13h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6400d 13h /
135 uart_address_0 was a latch -> changed ustadler 6401d 09h /
134 Added second test program for testing uart. jlechner 6401d 09h /
133 - Fixed bug with ST opcodes. cwalter 6401d 11h /
132 Added test program for testing uart. jlechner 6401d 11h /
131 Changed high active resets to low active ones. jlechner 6401d 11h /
130 Removed obsolete line jlechner 6401d 11h /
129 Sample assembler program for accessing uart jlechner 6401d 11h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6401d 11h /
127 Changed high active resets to low active ones. jlechner 6401d 11h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6401d 18h /
125 Fixed vhdl bugs trinklhar 6401d 18h /
124 Assigned UART signals to ports on top-level entity trinklhar 6401d 18h /
123 Removed UART again trinklhar 6401d 19h /
122 Removed UART again again trinklhar 6401d 19h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6401d 19h /
120 Added UART module to memory entity trinklhar 6401d 19h /
119 Uart wieder ausgebaut trinklhar 6402d 14h /
118 insert Uart address constant trinklhar 6402d 14h /
117 Uart im mem_stage trinklhar 6402d 14h /
116 writes to uart when write to reg 0 trinklhar 6403d 20h /
115 *** empty log message *** trinklhar 6404d 10h /
114 Uart 0.3 trinklhar 6405d 14h /
113 Uart reset funkt trinklhar 6405d 15h /
112 Uart drin aber signale nicht eingebunden trinklhar 6405d 17h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6408d 08h /
110 - Added missing file to CVS. cwalter 6408d 15h /
109 - Assembler code for ST produced wrong instruction format. cwalter 6409d 07h /

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