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Rev Log message Author Age Path
140 - Test bench for RISE with UART. cwalter 6361d 16h /
139 - Added makefile example to improve design flow.
- Added subroutine example.
cwalter 6361d 16h /
138 - Fixed binary to VHDL converter. cwalter 6361d 17h /
137 - Added binary to VHDL converter. cwalter 6361d 17h /
136 - Added makefile example to improve design flow.
- Added subroutine example.
cwalter 6361d 17h /
135 uart_address_0 was a latch -> changed ustadler 6362d 13h /
134 Added second test program for testing uart. jlechner 6362d 13h /
133 - Fixed bug with ST opcodes. cwalter 6362d 15h /
132 Added test program for testing uart. jlechner 6362d 15h /
131 Changed high active resets to low active ones. jlechner 6362d 15h /
130 Removed obsolete line jlechner 6362d 16h /
129 Sample assembler program for accessing uart jlechner 6362d 16h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.
jlechner 6362d 16h /
127 Changed high active resets to low active ones. jlechner 6362d 16h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6362d 22h /
125 Fixed vhdl bugs trinklhar 6362d 22h /
124 Assigned UART signals to ports on top-level entity trinklhar 6362d 22h /
123 Removed UART again trinklhar 6362d 23h /
122 Removed UART again again trinklhar 6362d 23h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6362d 23h /
120 Added UART module to memory entity trinklhar 6362d 23h /
119 Uart wieder ausgebaut trinklhar 6363d 18h /
118 insert Uart address constant trinklhar 6363d 18h /
117 Uart im mem_stage trinklhar 6363d 18h /
116 writes to uart when write to reg 0 trinklhar 6365d 01h /
115 *** empty log message *** trinklhar 6365d 15h /
114 Uart 0.3 trinklhar 6366d 19h /
113 Uart reset funkt trinklhar 6366d 20h /
112 Uart drin aber signale nicht eingebunden trinklhar 6366d 21h /
111 - Fixed bug where certain opcodes did not check for availability of
registers.
cwalter 6369d 13h /

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