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Rev Log message Author Age Path
146 - Changed to compile UART example. cwalter 6375d 01h /
145 - Added more VHDL files to project. cwalter 6375d 01h /
144 - IF stage now uses autogenerated VHDL files. cwalter 6375d 01h /
143 - Added more complex UART example. cwalter 6375d 01h /
142 - Added gap between characters sent and changed last character to CR. cwalter 6375d 01h /
141 - Added delay between characters. cwalter 6375d 01h /
140 - Test bench for RISE with UART. cwalter 6375d 01h /
139 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6375d 02h /
138 - Fixed binary to VHDL converter. cwalter 6375d 02h /
137 - Added binary to VHDL converter. cwalter 6375d 03h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6375d 03h /
135 uart_address_0 was a latch -> changed ustadler 6375d 23h /
134 Added second test program for testing uart. jlechner 6375d 23h /
133 - Fixed bug with ST opcodes. cwalter 6376d 01h /
132 Added test program for testing uart. jlechner 6376d 01h /
131 Changed high active resets to low active ones. jlechner 6376d 01h /
130 Removed obsolete line jlechner 6376d 01h /
129 Sample assembler program for accessing uart jlechner 6376d 01h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6376d 01h /
127 Changed high active resets to low active ones. jlechner 6376d 02h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6376d 08h /
125 Fixed vhdl bugs trinklhar 6376d 08h /
124 Assigned UART signals to ports on top-level entity trinklhar 6376d 08h /
123 Removed UART again trinklhar 6376d 09h /
122 Removed UART again again trinklhar 6376d 09h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6376d 09h /
120 Added UART module to memory entity trinklhar 6376d 09h /
119 Uart wieder ausgebaut trinklhar 6377d 04h /
118 insert Uart address constant trinklhar 6377d 04h /
117 Uart im mem_stage trinklhar 6377d 04h /

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