OpenCores
URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 147

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
147 - Updated to use current example. cwalter 6364d 04h /
146 - Changed to compile UART example. cwalter 6364d 06h /
145 - Added more VHDL files to project. cwalter 6364d 06h /
144 - IF stage now uses autogenerated VHDL files. cwalter 6364d 06h /
143 - Added more complex UART example. cwalter 6364d 06h /
142 - Added gap between characters sent and changed last character to CR. cwalter 6364d 06h /
141 - Added delay between characters. cwalter 6364d 07h /
140 - Test bench for RISE with UART. cwalter 6364d 07h /
139 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6364d 07h /
138 - Fixed binary to VHDL converter. cwalter 6364d 08h /
137 - Added binary to VHDL converter. cwalter 6364d 08h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6364d 08h /
135 uart_address_0 was a latch -> changed ustadler 6365d 04h /
134 Added second test program for testing uart. jlechner 6365d 04h /
133 - Fixed bug with ST opcodes. cwalter 6365d 06h /
132 Added test program for testing uart. jlechner 6365d 06h /
131 Changed high active resets to low active ones. jlechner 6365d 06h /
130 Removed obsolete line jlechner 6365d 07h /
129 Sample assembler program for accessing uart jlechner 6365d 07h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6365d 07h /
127 Changed high active resets to low active ones. jlechner 6365d 07h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6365d 13h /
125 Fixed vhdl bugs trinklhar 6365d 13h /
124 Assigned UART signals to ports on top-level entity trinklhar 6365d 13h /
123 Removed UART again trinklhar 6365d 14h /
122 Removed UART again again trinklhar 6365d 14h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6365d 14h /
120 Added UART module to memory entity trinklhar 6365d 14h /
119 Uart wieder ausgebaut trinklhar 6366d 09h /
118 insert Uart address constant trinklhar 6366d 09h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.