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Rev	Log message	Author	Age	Path
37	Applied VHDL indent.	jlechner	6413d 22h	/
36	- Testbench for RISE.	cwalter	6413d 22h	/
35	- Testbench for register file.	cwalter	6413d 22h	/
34	- Filex have been renamed to have tb prefix.	cwalter	6413d 22h	/
33	- Fixed process sensitivity list.	cwalter	6413d 23h	/
32	- When this stage asserts stall_out it must clear the input for the next stage. - Fixed process sensitivity list.	cwalter	6413d 23h	/
31	- Added PC_RESET_VECTOR constant.	cwalter	6414d 00h	/
30	- Top level testbench for RISE.	cwalter	6414d 00h	/
29	- Initial version of IF stage with dummy instructions.	cwalter	6414d 00h	/
28	Added new register write enable signals.	jlechner	6415d 18h	/
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6415d 18h	/
26	Applied VHDL indent.	jlechner	6415d 18h	/
25	netlist file for the memories is needed for IMEM and DMEM	ustadler	6416d 18h	/
24	4k Data Instruction for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6416d 18h	/
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6416d 18h	/
22	testbench für die register file	ustadler	6417d 07h	/
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6417d 19h	/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6417d 21h	/
19	Version 1.2 der register file	ustadler	6418d 04h	/
18	Update of pipeline schematics: - Fixed errors - Changed names of some signals so they are equal with VHDL code - Added second register lock port	jlechner	6419d 00h	/
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6420d 21h	/
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6420d 21h	/
15	- Added second register locking port reg_lock1. - Added function to check if the instruction modifies the SR register. - Fetch of SR now checks if the SR is modified and if yes the SR register is marked as locked. - Stall signal for pipeline is now generated correctly. - Stall input is now checked. If asserted the current output values are hold until the stall signal is deasserted.	cwalter	6420d 21h	/
14	- Renamed clear/set_reg_lock to clear/set_reg_lock0. - Added second register locking port reg_lock1.	cwalter	6420d 21h	/
13	- Testbench now implements a simple register file. - Added new tests for OPCODE_LD_DISP, OPCODE_LD_DISP_MS OPCODE_LD_REG.	cwalter	6423d 19h	/
12	- Added constant definitions for SR, PC and LR register.	cwalter	6423d 19h	/
11	- Added checks to test if a register has been locked. If it is locked and used in the decoded instruction the stall_out signal is asserted. - Added missing signals to process sensitivity list. - Fixed bug in rY decoding where the value of rZ was used. - Implemented opcode_modifies_rx.	cwalter	6423d 19h	/
10	- added testbench for load immediate and load immediate with high byte.	cwalter	6425d 22h	/
9	- added support for immediate value decoding. - opcode extender now works correctly for load immediate. needed special handling for the high byte bit. - conditional decoder needed special handling for high byte bit.	cwalter	6425d 23h	/
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6426d 02h	/

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