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Rev	Log message	Author	Age	Path
44	- Added another version of a register file which is a bit simplier.	cwalter	6388d 19h	/
43	Correct implementation of necessary unlocking signals that are conncted to register locking unit.	jlechner	6388d 19h	/
42	Modified input signals for register locking (testbench modifications): Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6388d 19h	/
41	Modified input signals for register locking: Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6388d 19h	/
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6388d 19h	/
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6388d 19h	/
38	Memory output signal is now passed on asynchronously to write back stage.	jlechner	6388d 19h	/
37	Applied VHDL indent.	jlechner	6388d 19h	/
36	- Testbench for RISE.	cwalter	6388d 19h	/
35	- Testbench for register file.	cwalter	6388d 19h	/
34	- Filex have been renamed to have tb prefix.	cwalter	6388d 19h	/
33	- Fixed process sensitivity list.	cwalter	6388d 20h	/
32	- When this stage asserts stall_out it must clear the input for the next stage. - Fixed process sensitivity list.	cwalter	6388d 20h	/
31	- Added PC_RESET_VECTOR constant.	cwalter	6388d 21h	/
30	- Top level testbench for RISE.	cwalter	6388d 21h	/
29	- Initial version of IF stage with dummy instructions.	cwalter	6388d 21h	/
28	Added new register write enable signals.	jlechner	6390d 15h	/
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6390d 15h	/
26	Applied VHDL indent.	jlechner	6390d 15h	/
25	netlist file for the memories is needed for IMEM and DMEM	ustadler	6391d 15h	/
24	4k Data Instruction for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6391d 15h	/
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6391d 15h	/
22	testbench für die register file	ustadler	6392d 04h	/
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6392d 16h	/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6392d 18h	/
19	Version 1.2 der register file	ustadler	6393d 01h	/
18	Update of pipeline schematics: - Fixed errors - Changed names of some signals so they are equal with VHDL code - Added second register lock port	jlechner	6393d 20h	/
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6395d 18h	/
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6395d 18h	/
15	- Added second register locking port reg_lock1. - Added function to check if the instruction modifies the SR register. - Fetch of SR now checks if the SR is modified and if yes the SR register is marked as locked. - Stall signal for pipeline is now generated correctly. - Stall input is now checked. If asserted the current output values are hold until the stall signal is deasserted.	cwalter	6395d 18h	/

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