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Rev Log message Author Age Path
75 Changed preprocessing for DC synthesis fafa1971 6087d 19h /
74 Updated filelists. fafa1971 6087d 19h /
73 New version of scripts for DC and to compile boot code fafa1971 6087d 19h /
72 Modified RAM address from 0x400C0 to 0x4C000 fafa1971 6094d 02h /
71 Added check for S1_ROOT set (suggested by lain.ux) fafa1971 6095d 02h /
70 Again, the setup file is linked rather than copied fafa1971 6102d 11h /
69 Now contains also the other file fafa1971 6102d 11h /
68 Merged with the DC setup file fafa1971 6102d 11h /
67 Now uses XG/Tcl syntax fafa1971 6104d 11h /
66 Modified to use XG syntax fafa1971 6104d 11h /
65 Version with undisclosed library names fafa1971 6104d 11h /
64 Initial version
B
C
C
Initial versioNCVS: ----------------------------------------------------------------------		 fafa1971 6104d 12h /
63 *** empty log message *** fafa1971 6104d 12h /
62 Documentation files updated to reflect the 3 different flavors of S1 Core fafa1971 6150d 10h /
61 Updated to latest version fafa1971 6150d 10h /
60 Now supports also Virtex5 devices fafa1971 6150d 10h /
59 Now it is just one line fafa1971 6150d 10h /
58 These were only symbolic links to remember where such these things were defined fafa1971 6150d 10h /
57 Latest version fafa1971 6150d 10h /
56 Updated from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6150d 10h /
55 Nobody remembers why these blackboxed files were required! fafa1971 6150d 10h /
54 Updated filelists fafa1971 6150d 10h /
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6150d 10h /
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6150d 10h /
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6236d 10h /
50 Changed library paths for XST from macrocell to behav. fafa1971 6252d 17h /
49 Now supports 3 versions: S1 Core ME/SE/EE. fafa1971 6259d 18h /
48 Updated with new OpenSPARC 1.4 list fafa1971 6301d 09h /
47 Updated with `define preprocessing for Xilinx XST synthesis fafa1971 6301d 09h /
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6301d 09h /

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