Rev |
Log message |
Author |
Age |
Path |
49 |
SdCmd: Send renamed to Valid |
rkastl |
4956d 11h |
/ |
48 |
Fix failed build on modelsim altera PE |
rkastl |
4956d 11h |
/ |
47 |
AddedSdVerificationTestbench to Makefile, refs #19. |
rkastl |
4956d 11h |
/ |
46 |
Verification: Working on basic functional verification, refs #19. |
rkastl |
4956d 11h |
/ |
45 |
SDCardModel: Receiving CMD0 implemented, refs #18 |
rkastl |
4956d 11h |
/ |
44 |
SdCardModel: Started with SV-Model |
rkastl |
4956d 11h |
/ |
43 |
SdCmd: Added default to output receiving, refs #16. |
rkastl |
4956d 11h |
/ |
42 |
SdCmd: Synthesis script fixed, refs #16 |
rkastl |
4956d 11h |
/ |
41 |
SdCmd: SdCmd synthesis added to Makefile, refs #16 |
rkastl |
4956d 11h |
/ |
40 |
SdCmd: Synthesis added, but not tested. refs #16 |
rkastl |
4956d 11h |
/ |
39 |
SdCmd: Works with complete sensitivity list, a test synthesis is advised, refs #16 |
rkastl |
4956d 11h |
/ |
38 |
SdCmd: Rewrite to records works. ioCmd in sensitivity list does not!
refs #16 |
rkastl |
4956d 11h |
/ |
37 |
SdCmd: using records, added a bug somewhere. refs #16 |
rkastl |
4956d 11h |
/ |
36 |
SdCmd: Testbench: Tristate cmd, refs #19 |
rkastl |
4956d 11h |
/ |
35 |
SdCmd: Sending CMD0 is correct, refs #19 |
rkastl |
4956d 11h |
/ |
34 |
Sd: SdCmd: Sending commands implemented, but not tested. refs #16. |
rkastl |
4956d 11h |
/ |
33 |
General: Script for fast creation of unit or package folder |
rkastl |
4956d 11h |
/ |
32 |
SD: Entity for the top level entity with a SD controller
SD: Started on the SdController entity. |
rkastl |
4956d 11h |
/ |
31 |
Makefile: $(quartus) has to be set individually |
rkastl |
4956d 11h |
/ |
30 |
Wishbone: No wave.do |
rkastl |
4956d 11h |
/ |
29 |
Sd: package started |
rkastl |
4956d 11h |
/ |
28 |
Wishbone: reads and writes as procedures in the tb |
rkastl |
4956d 11h |
/ |
27 |
Wishbone: Testbench tests a single ClassicRead |
rkastl |
4956d 11h |
/ |
26 |
Wishbone: Changed entity to reflect the real width of iAdr |
rkastl |
4956d 11h |
/ |
25 |
Wishbone: ClassicRead and ClassicWrite implemented, basic testbench
created |
rkastl |
4956d 11h |
/ |
24 |
Wishbone: Build fixed for splitted packages. |
rkastl |
4956d 11h |
/ |
23 |
Wishbone: Package split into a global and a specific one. |
rkastl |
4956d 11h |
/ |
22 |
Wishbone: Processes for statemachine created |
rkastl |
4956d 11h |
/ |
21 |
Wishbone: Control signals into records, unfortunately signals with a
width dependend on generics can not be used in records before VHDL2008. |
rkastl |
4956d 11h |
/ |
20 |
Wishbone: Directions added to port, support for synchronous cycle
termination added to entity (and therefore new types in the package were
created) |
rkastl |
4956d 11h |
/ |