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Rev Log message Author Age Path
94 CmdTimeout (8 Clocks) added, SdData inserted into top, refs #31 rkastl 4971d 19h /
93 Don´t run a full synthesis for SdData alone. It won´t fit. rkastl 4971d 19h /
92 SdData: Sending in standard and wide mode (incl. simple not automated
testbench and synthesis), refs #31.		 rkastl 4971d 19h /
91 Settings for tty. rkastl 4971d 19h /
90 Fixes the milestone ReadCID. It works with SD2.0 (non HC) card. rkastl 4971d 19h /
89 Fixes #27, R3 uses '1111111' as CRC. rkastl 4971d 19h /
88 Timeouts inserted, Sending Card status via Rs232 if changed rkastl 4971d 19h /
87 TbdSd: Baudrate set to 115200, refs #28 rkastl 4971d 19h /
86 Rs232Tx: testbench, refs #28 rkastl 4971d 19h /
85 Synthese: TbdSd refactored to enable sharing.
Sim: SdVerificationTestbench to new tcl script ported
SdController: TimeoutGenerator added, refs #27		 rkastl 4971d 19h /
84 SdController: Refactored rkastl 4971d 19h /
83 SdCmd: Refactored rkastl 4971d 19h /
82 Timeoutgenerator: Build fixed rkastl 4971d 19h /
81 SdCmd: Build fixed and converted to better version rkastl 4971d 19h /
80 Renamed *.vhd to *.vhdl in last commit. rkastl 4971d 19h /
79 Rs232Tx: added to TbdSd
TimeoutGenerator: written		 rkastl 4971d 19h /
78 Rs232Tx: implemented, but not tested rkastl 4971d 19h /
77 refs #25, synthesis works again rkastl 4971d 19h /
76 SdCmd: ioCmd, output registered, fixes #26 rkastl 4971d 19h /
75 Transfer to SbX, ref #17 rkastl 4971d 19h /
74 Testbed: All pins, refs #17 rkastl 4971d 19h /
73 Testbed: Pins.tcl into TbdSdsyn.tcl, refs #17 rkastl 4971d 19h /
72 TbdSdsyn: +Pins.tcl, refs #17 rkastl 4971d 19h /
71 Testbed added to synthesis builds rkastl 4971d 19h /
70 Testbed: Status leds rkastl 4971d 19h /
69 TbdSd synthesis rkastl 4971d 19h /
68 Testbed for SD-CORE, refs #17 rkastl 4971d 19h /
67 IP added rkastl 4971d 19h /
66 SdTop: Synthesis works rkastl 4971d 19h /
65 SdTop: all sd pins rkastl 4971d 19h /

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