URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 47

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Rev	Log message	Author	Age	Path
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4504d 18h	/
46	test bench upgrade + rtl cleanup	dinesha	4506d 19h	/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4506d 23h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4508d 21h	/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4508d 23h	/
42	Bug fix in read access is fixed	dinesha	4508d 23h	/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4509d 01h	/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4509d 18h	/
39	Test Bench upgradation with bigger data burst size	dinesha	4509d 18h	/
38	Port Name clean up	dinesha	4510d 23h	/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4511d 01h	/
36	Clean up	dinesha	4511d 15h	/
35	Updated the New Documents - ver 0.1	dinesha	4511d 17h	/
34	Removed the older version	dinesha	4511d 17h	/
33	clean up	dinesha	4511d 18h	/
32	Debug is enable through +define	dinesha	4513d 17h	/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4513d 17h	/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4513d 17h	/
29	SDRAM top and core related run file list are added into svn	dinesha	4513d 17h	/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4513d 17h	/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4514d 15h	/
26	invalid log files are removed	dinesha	4514d 15h	/
25	tb.sv is renamed as tb_top	dinesha	4514d 15h	/
24	Clean Up	dinesha	4514d 15h	/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4515d 20h	/
22	Pad sdram clock added	dinesha	4515d 21h	/
21	Clean up	dinesha	4515d 21h	/
20	8 Bit SDARM support is added	dinesha	4517d 15h	/
19	8 Bit SDRAM Support added	dinesha	4517d 15h	/
18	8 Bit SDRAM Support is added	dinesha	4517d 15h	/

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Subversion Repositories sdr_ctrl

[/] - Rev 47

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