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Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4374d 03h /
65 Updated Log file with CAS latency support 4,5 dinesha 4374d 10h /
64 CAS Latency support added for 4,5 dinesha 4374d 10h /
63 FPGA Bench mark results are added dinesha 4493d 09h /
62 Synthesis constraint for simplify dinesha 4493d 10h /
61 RTL file list are added into SVN dinesha 4493d 10h /
60 warning cleanup dinesha 4493d 10h /
59 Control path request and data are register now for better FPGA timing dinesha 4493d 10h /
58 Read Data is register on RD_FAST=0 case dinesha 4493d 10h /
57 Synthesis constraints are added dinesha 4494d 01h /
56 FPGA Synth optimisation dinesha 4494d 02h /
55 FPGA Synthesis timing optimisation dinesha 4494d 02h /
54 FPGA Timing Optimisation dinesha 4497d 00h /
53 Test bench upgradation dinesha 4498d 00h /
52 Documentation update for request control and transfer control block dinesha 4498d 00h /
51 FPGA relating timing optimisation done dinesha 4498d 01h /
50 Bug fix the request length is fixe dinesha 4500d 04h /
49 clean up dinesha 4501d 03h /
48 top-level cleanup dinesha 4501d 03h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4501d 04h /
46 test bench upgrade + rtl cleanup dinesha 4503d 04h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4503d 09h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4505d 07h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4505d 08h /
42 Bug fix in read access is fixed dinesha 4505d 08h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4505d 10h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4506d 03h /
39 Test Bench upgradation with bigger data burst size dinesha 4506d 03h /
38 Port Name clean up dinesha 4507d 08h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4507d 10h /

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