URL https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk

Subversion Repositories simple_fm_receiver

[/] - Rev 23

Rev	Log message	Author	Age	Path
23	Disable clear signal.	arif_endro	5878d 17h	/
22	Update last bit output assignment method.	arif_endro	5878d 17h	/
21	This commit was manufactured by cvs2svn to create tag 'version_1_1'.		7063d 18h	/
20	New Version	arif_endro	7063d 18h	/
19	Screen shot from chipscope analyzer view, this is how this design work.	arif_endro	7069d 17h	/
18	This bit files generates better wave than previous (i.e. more smooth)	arif_endro	7069d 19h	/
17	Initial Checkin	arif_endro	7077d 16h	/
16	Changes constan and minor fix	arif_endro	7080d 19h	/
15	Xilinx FPGA XC2V2000 bit files the first version.	arif_endro	7083d 17h	/
14	* empty log message *	arif_endro	7088d 15h	/
13	Update License	arif_endro	7099d 16h	/
12	Update License Change reset signal handle	arif_endro	7099d 17h	/
11	Update License Change reset signal handle	arif_endro	7099d 17h	/
10	Added script for generating cos ROM.	arif_endro	7109d 19h	/
9	Added documentation	arif_endro	7126d 18h	/
8	This commit was manufactured by cvs2svn to create tag 'okinawa_1'.		7140d 19h	/
7	To view chipscope exported output using ModelSim waveform window	arif_endro	7140d 19h	/
6	Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO)	arif_endro	7141d 21h	/
5	Added interface in/out and testing paralelly (e.g. square and triangular)	arif_endro	7141d 21h	/
4	Fix elsif and if statement	arif_endro	7144d 14h	/
3	This commit was manufactured by cvs2svn to create tag 'VSFR_1'.		7147d 21h	/
2	Initial releases	arif_endro	7147d 21h	/
1	Standard project directories initialized by cvs2svn.		7147d 21h	/