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Subversion Repositories socgen

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Rev Log message Author Age Path
70 ignore work jt_eaton 5024d 23h /
69 added work dir jt_eaton 5024d 23h /
68 moved to seperate components jt_eaton 5027d 23h /
67 updated installs jt_eaton 5027d 23h /
66 converted sims to use parameters
added msp and 6502 software installs
jt_eaton 5028d 22h /
65 added params.sim to sims
updated install's
jt_eaton 5033d 23h /
64 added support for Fedora 13 jt_eaton 5037d 22h /
63 added install config for Ubuntu 10.10 jt_eaton 5038d 04h /
62 fixed parameters from `defines jt_eaton 5041d 20h /
61 now generate dut files for coverage
removed use of lndir
jt_eaton 5041d 22h /
60 moved alu_logic into seperate component jt_eaton 5042d 09h /
59 added filelist.core to syn dirs to customize core jt_eaton 5042d 09h /
58 removed old Makefiles jt_eaton 5043d 00h /
57 Now generate all filelists from xml files jt_eaton 5043d 01h /
56 soc_builder now builds verilog from xml files jt_eaton 5048d 09h /
55 removed pre-rout and gates sims jt_eaton 5051d 05h /
54 now set up fpga targets from xml files jt_eaton 5051d 07h /
53 fixed check_fpgas jt_eaton 5053d 20h /
52 removed noworking sims and syn jt_eaton 5053d 21h /
51 removed old test jt_eaton 5053d 21h /
50 clean up from last checkin jt_eaton 5053d 21h /
49 added covered code coverage
added xml descriptors
added soc_Link tool
jt_eaton 5054d 00h /
48 added support for covered code checking jt_eaton 5076d 06h /
47 removed old variant jt_eaton 5090d 09h /
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v
jt_eaton 5090d 09h /
45 added 6502 sims/software and synth jt_eaton 5097d 05h /
44 added new parts and sw for 6502 jt_eaton 5097d 08h /
43 complete rework of states and sequencer
added interrupts
moved prog space and vectors to F space
jt_eaton 5107d 07h /
42 removed old versions that used prog as C space jt_eaton 5107d 07h /
41 added kim-1 design and program
now support Nexys2 sdram
jt_eaton 5125d 08h /

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