URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] - Rev 24

Rev	Log message	Author	Age	Path
24	Removing altera quartus 16.0	redbear	2579d 03h	/
23	FPGA verilog and corrections.	redbear	2608d 03h	/
22	Adding files work to altera fpga DE0 NANO SOC.	redbear	2608d 03h	/
21	Vpi data rx.	redbear	2629d 03h	/
20	SystemC minor correction.	redbear	2629d 03h	/
19	RX and TX correct.	redbear	2629d 03h	/
18	FSM minor correction	redbear	2636d 02h	/
17	TX correction FCT reaceive and TX data transfer.	redbear	2636d 02h	/
16	Adding TX_WRITE to go down after detect first edge posedge tx_ready.	redbear	2636d 02h	/
15	Tx with FCT with partial correction.	redbear	2664d 03h	/
14	New version of Receiver.	redbear	2664d 03h	/
13	upating files.	redbear	2691d 03h	/
12	update files and SystemC.	redbear	2713d 04h	/
11	Adding shared object.	redbear	2723d 04h	/
10	Update tx verilog rx systemc test.	redbear	2723d 04h	/
9	Update shared object and Graphical interface.	redbear	2723d 04h	/
8	EOPDATA is functional.	redbear	2723d 04h	/
7	Updating testbench file using correcting signals VPI.	redbear	2728d 06h	/
6	Updating FCT and NCHAR counters on TX.	redbear	2728d 06h	/
5	Adding first verilog with new struct dir.	redbear	2740d 05h	/
4	Deleting all	redbear	2740d 05h	/
3	Adding a tutorial about the use of SpaceWire Test Suit.	redbear	2905d 09h	/
2	initial work with spacewire	redbear	2913d 18h	/
1	The project and the structure was created	root	2914d 09h	/