URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] - Rev 34

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Rev	Log message	Author	Age	Path
34	Adding new fifo version rx/tx and tx spacewire.	redbear	2476d 22h	/
33	Updating with corrections and additions.	redbear	2491d 03h	/
32	Updating Altera De0 to work with fifos.	redbear	2491d 03h	/
31	Adding compile stage to SystemC	redbear	2584d 17h	/
30	Adding systemC environmment api	redbear	2584d 17h	/
29	Adding systemC environmment model SpaceWire.	redbear	2584d 17h	/
28	Adding version altera quatus lite 17.0.	redbear	2584d 17h	/
27	Adding write axi and updating files.	redbear	2584d 17h	/
26	Adding write axi and updating files.	redbear	2584d 17h	/
25	Updating	redbear	2584d 17h	/
24	Removing altera quartus 16.0	redbear	2584d 18h	/
23	FPGA verilog and corrections.	redbear	2613d 17h	/
22	Adding files work to altera fpga DE0 NANO SOC.	redbear	2613d 18h	/
21	Vpi data rx.	redbear	2634d 17h	/
20	SystemC minor correction.	redbear	2634d 17h	/
19	RX and TX correct.	redbear	2634d 17h	/
18	FSM minor correction	redbear	2641d 16h	/
17	TX correction FCT reaceive and TX data transfer.	redbear	2641d 16h	/
16	Adding TX_WRITE to go down after detect first edge posedge tx_ready.	redbear	2641d 16h	/
15	Tx with FCT with partial correction.	redbear	2669d 17h	/
14	New version of Receiver.	redbear	2669d 17h	/
13	upating files.	redbear	2696d 17h	/
12	update files and SystemC.	redbear	2718d 18h	/
11	Adding shared object.	redbear	2728d 18h	/
10	Update tx verilog rx systemc test.	redbear	2728d 18h	/
9	Update shared object and Graphical interface.	redbear	2728d 18h	/
8	EOPDATA is functional.	redbear	2728d 18h	/
7	Updating testbench file using correcting signals VPI.	redbear	2733d 20h	/
6	Updating FCT and NCHAR counters on TX.	redbear	2733d 20h	/
5	Adding first verilog with new struct dir.	redbear	2745d 19h	/

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Subversion Repositories spacewiresystemc

[/] - Rev 34

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