OpenCores
URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] - Rev 38

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
38 Signal renaming and bug fix. gedra 7346d 12h /
37 Converted to numeric_std and fixed a few bugs. gedra 7347d 14h /
36 Top level entity for receiver. gedra 7347d 14h /
35 Top level test bench for receiver. NB! Not complete. gedra 7347d 14h /
34 Converter to numeric_std and added hex functions gedra 7347d 14h /
33 Minor update. gedra 7347d 14h /
32 Wishbone bus utilities. gedra 7349d 09h /
31 Added data output. gedra 7349d 09h /
30 Added Wishbone bus cycle decoder. gedra 7350d 10h /
29 Wishbone bus cycle decoder. gedra 7350d 10h /
28 Delint'ed and changed name of architecture. gedra 7354d 19h /
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7355d 10h /
26 Fixed a few bugs. gedra 7357d 10h /
25 Changed status reg. declaration gedra 7357d 10h /
24 Added channel status decoding. gedra 7357d 10h /
23 Added frame decoder gedra 7357d 10h /
22 Renamed generic gedra 7360d 10h /
21 Renamed generic's and modified recevier configuration register gedra 7360d 10h /
20 Renamed generic and cleaned some lint's gedra 7360d 10h /
19 Added frame decoder and sample extractor gedra 7360d 10h /
18 Frame decoder and sample extractor gedra 7360d 10h /
17 Cleaned up lint warnings. gedra 7363d 10h /
16 Added dual port ram. gedra 7364d 09h /
15 Generic dual port ram model. gedra 7364d 09h /
14 Receiver component declarations. gedra 7366d 10h /
13 Cleaned up lint warnings. gedra 7367d 13h /
12 Simple test bench for rx_phase_det.vhd. gedra 7367d 13h /
11 Early version of the bi-phase mark decoder. gedra 7367d 13h /
10 Recevier status register gedra 7368d 11h /
9 Channel status/user data capture register gedra 7368d 11h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.