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Rev Log message Author Age Path
44 Transmitter Wishbone bus cycle decoder. gedra 7291d 03h /
43 This commit was manufactured by cvs2svn to create tag 'rx_beta_1'. 7292d 04h /
42 Fixed bug with lock event generation. gedra 7292d 04h /
41 Test bench update. gedra 7292d 04h /
40 Improved test bench. gedra 7293d 05h /
39 Bug-fix. gedra 7293d 05h /
38 Signal renaming and bug fix. gedra 7307d 05h /
37 Converted to numeric_std and fixed a few bugs. gedra 7308d 07h /
36 Top level entity for receiver. gedra 7308d 07h /
35 Top level test bench for receiver. NB! Not complete. gedra 7308d 07h /
34 Converter to numeric_std and added hex functions gedra 7308d 07h /
33 Minor update. gedra 7308d 07h /
32 Wishbone bus utilities. gedra 7310d 02h /
31 Added data output. gedra 7310d 02h /
30 Added Wishbone bus cycle decoder. gedra 7311d 03h /
29 Wishbone bus cycle decoder. gedra 7311d 03h /
28 Delint'ed and changed name of architecture. gedra 7315d 12h /
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7316d 03h /
26 Fixed a few bugs. gedra 7318d 02h /
25 Changed status reg. declaration gedra 7318d 02h /
24 Added channel status decoding. gedra 7318d 02h /
23 Added frame decoder gedra 7318d 02h /
22 Renamed generic gedra 7321d 03h /
21 Renamed generic's and modified recevier configuration register gedra 7321d 03h /
20 Renamed generic and cleaned some lint's gedra 7321d 03h /
19 Added frame decoder and sample extractor gedra 7321d 03h /
18 Frame decoder and sample extractor gedra 7321d 03h /
17 Cleaned up lint warnings. gedra 7324d 02h /
16 Added dual port ram. gedra 7325d 02h /
15 Generic dual port ram model. gedra 7325d 02h /

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