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Rev Log message Author Age Path
50 Added string type casting to make ModelSim happy. gedra 7291d 15h /
49 Changed write signal for status buffers. gedra 7292d 15h /
48 Added new components. gedra 7292d 15h /
47 Transmitter channel status buffer. gedra 7292d 15h /
46 Transmitter version register. gedra 7292d 15h /
45 Transmitter component declarations. gedra 7293d 14h /
44 Transmitter Wishbone bus cycle decoder. gedra 7293d 14h /
43 This commit was manufactured by cvs2svn to create tag 'rx_beta_1'. 7294d 16h /
42 Fixed bug with lock event generation. gedra 7294d 16h /
41 Test bench update. gedra 7294d 16h /
40 Improved test bench. gedra 7295d 17h /
39 Bug-fix. gedra 7295d 17h /
38 Signal renaming and bug fix. gedra 7309d 17h /
37 Converted to numeric_std and fixed a few bugs. gedra 7310d 19h /
36 Top level entity for receiver. gedra 7310d 19h /
35 Top level test bench for receiver. NB! Not complete. gedra 7310d 19h /
34 Converter to numeric_std and added hex functions gedra 7310d 19h /
33 Minor update. gedra 7310d 19h /
32 Wishbone bus utilities. gedra 7312d 13h /
31 Added data output. gedra 7312d 13h /
30 Added Wishbone bus cycle decoder. gedra 7313d 15h /
29 Wishbone bus cycle decoder. gedra 7313d 15h /
28 Delint'ed and changed name of architecture. gedra 7317d 23h /
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7318d 14h /
26 Fixed a few bugs. gedra 7320d 14h /
25 Changed status reg. declaration gedra 7320d 14h /
24 Added channel status decoding. gedra 7320d 14h /
23 Added frame decoder gedra 7320d 14h /
22 Renamed generic gedra 7323d 15h /
21 Renamed generic's and modified recevier configuration register gedra 7323d 15h /

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