URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] - Rev 58

Rev	Log message	Author	Age	Path
58	Fixed bug.	gedra	7258d 08h	/
57	Added component.	gedra	7258d 08h	/
56	Transmitter SPDIF encoder.	gedra	7258d 08h	/
55	Top level testbench for transmitter and receiver.	gedra	7258d 08h	/
54	Improved test bench package.	gedra	7258d 08h	/
53	Fixed bug.	gedra	7260d 07h	/
52	Changed address of channel status buffers.	gedra	7260d 07h	/
51	Changed two interrupts in the transmitter.	gedra	7261d 05h	/
50	Added string type casting to make ModelSim happy.	gedra	7262d 07h	/
49	Changed write signal for status buffers.	gedra	7263d 07h	/
48	Added new components.	gedra	7263d 07h	/
47	Transmitter channel status buffer.	gedra	7263d 07h	/
46	Transmitter version register.	gedra	7263d 07h	/
45	Transmitter component declarations.	gedra	7264d 06h	/
44	Transmitter Wishbone bus cycle decoder.	gedra	7264d 06h	/
43	This commit was manufactured by cvs2svn to create tag 'rx_beta_1'.		7265d 07h	/
42	Fixed bug with lock event generation.	gedra	7265d 07h	/
41	Test bench update.	gedra	7265d 07h	/
40	Improved test bench.	gedra	7266d 08h	/
39	Bug-fix.	gedra	7266d 08h	/
38	Signal renaming and bug fix.	gedra	7280d 08h	/
37	Converted to numeric_std and fixed a few bugs.	gedra	7281d 10h	/
36	Top level entity for receiver.	gedra	7281d 10h	/
35	Top level test bench for receiver. NB! Not complete.	gedra	7281d 10h	/
34	Converter to numeric_std and added hex functions	gedra	7281d 10h	/
33	Minor update.	gedra	7281d 10h	/
32	Wishbone bus utilities.	gedra	7283d 05h	/
31	Added data output.	gedra	7283d 05h	/
30	Added Wishbone bus cycle decoder.	gedra	7284d 06h	/
29	Wishbone bus cycle decoder.	gedra	7284d 06h	/