URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] - Rev 27

Rev	Log message	Author	Age	Path
27	connect missing input direction for IO G	arniml	6693d 01h	/
26	fix org for page 11 in COP420 code	arniml	6693d 01h	/
25	fix wrong aisc commands	arniml	6693d 02h	/
24	finalize test	arniml	6693d 03h	/
23	finalize test	arniml	6693d 18h	/
22	finish test	arniml	6694d 02h	/
21	include t420 system and testbench	arniml	6694d 03h	/
20	initial check-in	arniml	6694d 03h	/
19	moved elements to separate design unit tb_elems	arniml	6694d 04h	/
18	initial check-in	arniml	6694d 04h	/
17	remove direct specification of cpu type	arniml	6695d 03h	/
16	enabled t420 support	arniml	6695d 03h	/
15	initial check-in	arniml	6695d 03h	/
14	t420 hierarchies added	arniml	6695d 03h	/
13	hand-down clock divider option	arniml	6701d 23h	/
12	fix sensitivity list	arniml	6702d 23h	/
11	renamed to rtl	arniml	6703d 00h	/
10	renamed t400_por configuration to rtl	arniml	6703d 00h	/
9	initial check-in	arniml	6703d 00h	/
8	phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o	arniml	6703d 12h	/
7	remove delta cycle filter on sk_s	arniml	6703d 12h	/
6	initial check-in	arniml	6703d 13h	/
5	initial check-in	arniml	6704d 00h	/
4	remove superfluous testbench	arniml	6704d 00h	/
3	This commit was manufactured by cvs2svn to create tag 'LOC_CVS_0_1'.		6704d 00h	/
2	import from local CVS repository, LOC_CVS_0_1	arniml	6704d 00h	/
1	Standard project directories initialized by cvs2svn.		6704d 00h	/