URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] - Rev 79

Rev	Log message	Author	Age	Path
79	enhance save and restore for A, M and C	arniml	6694d 23h	/
78	provide SA at L port	arniml	6695d 10h	/
77	initial check-in	arniml	6695d 10h	/
76	remove tb_int_behav_c0	arniml	6695d 10h	/
75	initial check-in	arniml	6695d 10h	/
74	add interrupt testbench and 'int' test class	arniml	6695d 14h	/
73	use 'after' instead of wait for signal delay should resolve problems with delta cycle arrival times	arniml	6695d 14h	/
72	make test start more robust regarding timing	arniml	6695d 14h	/
71	obsolete	arniml	6695d 17h	/
70	interrupt functionality added	arniml	6695d 17h	/
69	instrument testbench	arniml	6695d 17h	/
68	updates for interrupt support	arniml	6695d 17h	/
67	explicitly select clock divider 4	arniml	6695d 17h	/
66	explicitly select clock divider 8	arniml	6695d 17h	/
65	add global signals for testbench instrumentation	arniml	6695d 17h	/
64	add fail reporting for port d	arniml	6695d 17h	/
63	initial check-in	arniml	6695d 17h	/
62	int target added	arniml	6695d 18h	/
61	initial check-in	arniml	6697d 21h	/
60	connect cko_i to bit 2 of IN bus	arniml	6699d 12h	/
59	check CKO in general purpose configuration	arniml	6699d 12h	/
58	consider IN port	arniml	6700d 11h	/
57	consider CKO and IN port	arniml	6700d 11h	/
56	drive IN port	arniml	6700d 11h	/
55	routi CKO to t400_core	arniml	6700d 11h	/
54	use to_X01 for primary input bus	arniml	6700d 11h	/
53	use to_X01 for G input	arniml	6700d 11h	/
52	+ reset neg_edge flip-flops to '1' -> after por, a 1-to-0 edge is required to trigger the latches initially + use to_X01	arniml	6700d 11h	/
51	initial check-in	arniml	6700d 11h	/
50	initial check-in	arniml	6700d 13h	/