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URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

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Rev Log message Author Age Path
110 exchange syn_rom for lpm_rom arniml 7362d 06h /
109 add new bug for release 0.1 BETA arniml 7362d 19h /
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7362d 19h /
107 tie EA to '1' arniml 7362d 19h /
106 clean-up use of ea_i arniml 7362d 20h /
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7365d 05h /
104 add white_box directory to test suite arniml 7366d 03h /
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7366d 03h /
102 update for changes in address space of external memory arniml 7366d 03h /
101 assert p2_read_p2_o when expander port is read arniml 7366d 03h /
100 reorder data_o generation arniml 7366d 03h /
99 initial check-in arniml 7366d 03h /
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7366d 03h /
97 initial check-in arniml 7366d 04h /
96 select dedicated directorie(s) for regression arniml 7367d 01h /
95 check counter inactivity arniml 7367d 01h /
94 initial check-in arniml 7367d 01h /
93 add support for line coverage evaluation with gcov arniml 7367d 02h /
92 work around bug in Quartus II 4.0 arniml 7367d 02h /
91 fix edge detector bug for counter arniml 7367d 02h /
90 intial check-in arniml 7367d 02h /
89 initial check-in arniml 7380d 22h /
88 allow memory bank switching during interrupts arniml 7382d 00h /
87 abort gracfullt if memory bank switching does not work arniml 7382d 00h /
86 update notice about expander port instructions arniml 7382d 05h /
85 initial check-in arniml 7382d 05h /
84 add if_timing module arniml 7387d 21h /
83 connect if_timing to P2 output of T48 arniml 7387d 21h /
82 check expander timings arniml 7387d 21h /
81 initial check-in arniml 7388d 01h /

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