URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

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Rev	Log message	Author	Age	Path
163	add bug Wrong clock applied to T0	arniml	6996d 17h	/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	6996d 17h	/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7027d 21h	/
160	add others to case statement	arniml	7148d 17h	/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7148d 17h	/
158	added hierarchies t8039_notri and t8048_notri	arniml	7148d 17h	/
157	removed obsolete constant	arniml	7148d 18h	/
156	added hierarchy t8039_notri	arniml	7148d 18h	/
155	initial check-in	arniml	7148d 18h	/
154	added t8039_notri hierarchy	arniml	7148d 18h	/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7149d 15h	/
152	added hierarchy t8048_notri and system components package	arniml	7150d 06h	/
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7150d 06h	/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7150d 14h	/
149	update	arniml	7150d 14h	/
148	initial check-in	arniml	7150d 14h	/
147	initial check-in for release 0.5 BETA	arniml	7186d 16h	/
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7187d 16h	/
145	remove PROG and end of XTAL2, see comment for details	arniml	7187d 17h	/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7187d 17h	/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7187d 18h	/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7187d 18h	/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7187d 18h	/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7187d 18h	/
139	add bug P1 constantly in push-pull mode in t8048	arniml	7189d 04h	/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7189d 04h	/
137	add link to COMPILE_LIST	arniml	7226d 17h	/
136	initial check-in	arniml	7226d 17h	/
135	add bug PSENn Timing	arniml	7231d 03h	/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7231d 13h	/

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Subversion Repositories t48

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