Rev |
Log message |
Author |
Age |
Path |
169 |
initial check-in |
arniml |
7040d 07h |
/ |
168 |
change address range of wb_master |
arniml |
7040d 07h |
/ |
167 |
simplify address range:
- configuration range
- Wishbone range |
arniml |
7040d 07h |
/ |
166 |
assign default for state_s |
arniml |
7041d 23h |
/ |
165 |
add component wb_master.vhd |
arniml |
7042d 22h |
/ |
164 |
initial check-in |
arniml |
7042d 22h |
/ |
163 |
add bug
Wrong clock applied to T0 |
arniml |
7043d 21h |
/ |
162 |
Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i |
arniml |
7043d 21h |
/ |
161 |
fix syntax problem that triggers an error with GHDL 0.18 |
arniml |
7075d 01h |
/ |
160 |
add others to case statement |
arniml |
7195d 21h |
/ |
159 |
fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 |
arniml |
7195d 22h |
/ |
158 |
added hierarchies t8039_notri and t8048_notri |
arniml |
7195d 22h |
/ |
157 |
removed obsolete constant |
arniml |
7195d 22h |
/ |
156 |
added hierarchy t8039_notri |
arniml |
7195d 22h |
/ |
155 |
initial check-in |
arniml |
7195d 22h |
/ |
154 |
added t8039_notri hierarchy |
arniml |
7195d 22h |
/ |
153 |
introduced generic gate_port_input_g
forces masking of P1 and P2 input bus |
arniml |
7196d 19h |
/ |
152 |
added hierarchy t8048_notri and system components package |
arniml |
7197d 10h |
/ |
151 |
added hierarchy t8048_notri and components package for t48 systems |
arniml |
7197d 10h |
/ |
150 |
intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled |
arniml |
7197d 18h |
/ |
149 |
update |
arniml |
7197d 18h |
/ |
148 |
initial check-in |
arniml |
7197d 18h |
/ |
147 |
initial check-in for release 0.5 BETA |
arniml |
7233d 20h |
/ |
146 |
add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A |
arniml |
7234d 20h |
/ |
145 |
remove PROG and end of XTAL2, see comment for details |
arniml |
7234d 21h |
/ |
144 |
delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR' |
arniml |
7234d 21h |
/ |
143 |
Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle |
arniml |
7234d 22h |
/ |
142 |
deassert rd_q, wr_q and prog_q at end of XTAL3 |
arniml |
7234d 22h |
/ |
141 |
disable external memory to avoid conflicts with outl a, bus |
arniml |
7234d 22h |
/ |
140 |
remove tAW sanity check
conflicts with OUTL A, BUS |
arniml |
7234d 22h |
/ |