URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 93

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Rev	Log message	Author	Age	Path
93	add support for line coverage evaluation with gcov	arniml	7366d 18h	/
92	work around bug in Quartus II 4.0	arniml	7366d 18h	/
91	fix edge detector bug for counter	arniml	7366d 18h	/
90	intial check-in	arniml	7366d 18h	/
89	initial check-in	arniml	7380d 14h	/
88	allow memory bank switching during interrupts	arniml	7381d 16h	/
87	abort gracfullt if memory bank switching does not work	arniml	7381d 16h	/
86	update notice about expander port instructions	arniml	7381d 21h	/
85	initial check-in	arniml	7381d 21h	/
84	add if_timing module	arniml	7387d 12h	/
83	connect if_timing to P2 output of T48	arniml	7387d 13h	/
82	check expander timings	arniml	7387d 13h	/
81	initial check-in	arniml	7387d 17h	/
80	added if_timing	arniml	7387d 17h	/
79	add if_timing module	arniml	7387d 17h	/
78	adjust external timing of BUS	arniml	7387d 17h	/
77	move from std_logic_arith to numeric_std	arniml	7388d 09h	/
76	initial check-in	arniml	7388d 13h	/
75	remove obsolete design unit	arniml	7388d 13h	/
74	enhance pass/fail detection	arniml	7388d 22h	/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7388d 22h	/
72	removed superfluous signal from sensitivity list	arniml	7388d 22h	/
71	add T8039 and its testbench	arniml	7394d 14h	/
70	clean test cell before make	arniml	7394d 14h	/
69	fix name of istrobe	arniml	7394d 14h	/
68	connect T0 and T1 to P1	arniml	7394d 14h	/
67	initial check-in	arniml	7394d 14h	/
66	add temporary workaround for GHDL 0.11	arniml	7394d 14h	/
65	clean up sensitivity list	arniml	7394d 14h	/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7394d 14h	/

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Subversion Repositories t48

[/] - Rev 93

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