URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] - Rev 27

Rev	Log message	Author	Age	Path
27	Xilinx SSRAM, initial release	jesus	7972d 09h	/
26	Fixed instruction timing for POP and DJNZ	jesus	7986d 00h	/
25	IX/IY timing and ADC/SBC fix	jesus	7987d 10h	/
24	no message	jesus	7993d 07h	/
23	Fixed T2Write	jesus	7993d 07h	/
22	Added 8080 top level	jesus	7993d 07h	/
21	no message	jesus	7998d 06h	/
20	Updated for new T80s generic	jesus	7998d 06h	/
19	Initial version	jesus	7998d 06h	/
18	Added T2Write generic	jesus	7998d 13h	/
17	Removed write through	jesus	8000d 06h	/
16	no message	jesus	8000d 09h	/
15	Added clock enable and fixed IM 2	jesus	8007d 09h	/
14	Changed to Xilinx ROM	jesus	8026d 20h	/
13	Initial import	jesus	8026d 20h	/
12	Initial import	jesus	8026d 21h	/
11	Added support for XST	jesus	8026d 21h	/
10	Added dummy files	jesus	8026d 22h	/
9	Initial import	jesus	8028d 08h	/
8	Fixed refresh address and DJNZ instruction	jesus	8028d 09h	/
7	Initial import	jesus	8028d 10h	/
6	Fixed wide rom .ucf generation	jesus	8105d 10h	/
5	Now it seems to work	jesus	8105d 10h	/
4	Fixed xilinx ROM generation	jesus	8106d 13h	/
3	Initial commit, incomplete	jesus	8108d 15h	/
2	Initial import	jesus	8124d 00h	/
1	Standard project directories initialized by cvs2svn.		8124d 00h	/