Rev |
Log message |
Author |
Age |
Path |
26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4412d 20h |
/ |
25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4413d 00h |
/ |
24 |
Good news, mov to IP actually works as expected! |
earlz |
4413d 17h |
/ |
23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4413d 18h |
/ |
22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4414d 10h |
/ |
21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4414d 10h |
/ |
20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4415d 10h |
/ |
19 |
Got beginning of core/decoder for the CPU |
earlz |
4415d 11h |
/ |
18 |
Finished memory controller |
earlz |
4418d 21h |
/ |
17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4419d 10h |
/ |
16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4422d 13h |
/ |
15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4424d 10h |
/ |
14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4424d 18h |
/ |
13 |
Forgot about the new library I added |
earlz |
4424d 21h |
/ |
12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4424d 22h |
/ |
11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4428d 11h |
/ |
10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4428d 11h |
/ |
9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4428d 19h |
/ |
8 |
Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing |
earlz |
4429d 19h |
/ |
7 |
Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000) |
earlz |
4429d 20h |
/ |
6 |
Reworked memory code to hopefully synthesize better |
earlz |
4430d 00h |
/ |
5 |
Modified registerfile to be dual-port for both read and write |
earlz |
4430d 11h |
/ |
4 |
Added internal memory interface
Updated design |
earlz |
4430d 19h |
/ |
3 |
Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming |
earlz |
4431d 11h |
/ |
2 |
Initial commit |
earlz |
4431d 12h |
/ |
1 |
The project and the structure was created |
root |
4431d 15h |
/ |