URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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Rev	Log message	Author	Age	Path
86	Added old uploaded documents to new repository.	root	5588d 16h	/
85	Added old uploaded documents to new repository.	root	5588d 22h	/
84	New directory structure.	root	5588d 22h	/
83	Some fixes from Guy-- replace case with casex.	hharte	5662d 04h	/
82	Clean up spacing	hharte	5672d 00h	/
81	Initial version of TV80 Wishbone Wrapper	hharte	5672d 01h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6771d 13h	/
79	Added JR self-checking test	ghutchis	6771d 13h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6814d 14h	/
77	Added back files lost after server crash	ghutchis	6846d 08h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6925d 14h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6925d 14h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6925d 16h	/
73	Added RC4 encrypt/decrypt test	ghutchis	6937d 10h	/
72	Added copyright header	ghutchis	6937d 10h	/
71	Ported UART from T80	ghutchis	6998d 14h	/
70	Added test for T16450 UART	ghutchis	7049d 09h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7049d 09h	/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7057d 10h	/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7057d 10h	/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7057d 10h	/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7057d 10h	/
64	Created rgen script and expanded available register types	ghutchis	7058d 08h	/
63	Added simple regression script. -r command runs all tests (serially), -c command checks results after all tests have completed.	ghutchis	7092d 13h	/
62	Reset timeout counter whenever a message is printed	ghutchis	7092d 13h	/
61	Added timeout disable for large buf sizes	ghutchis	7092d 13h	/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7092d 13h	/
59	Added lib for generating MPU interfaces	ghutchis	7092d 13h	/
58	Made TX path async Made TX clock input instead of output	ghutchis	7132d 01h	/
57	Optimized read-back of data using INIR instruction	ghutchis	7132d 07h	/

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Subversion Repositories tv80

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