URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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Rev	Log message	Author	Age	Path
94	Ported over env_io.v from Verilog environment to tv_responder. Basic tests from Verilog environment (hello, fib) now passing in SystemC environment.	ghutchis	5324d 20h	/
93	Added common header file for all systemc environment	ghutchis	5325d 18h	/
92	Added responder to top level, beginning of support for ihex load	ghutchis	5329d 19h	/
91	Preliminary support for SystemC/Verilator environment	ghutchis	5329d 22h	/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5329d 22h	/
89	RTL and environment fixes for nmi bug	ghutchis	5350d 01h	/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5351d 15h	/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5366d 23h	/
86	Added old uploaded documents to new repository.	root	5590d 05h	/
85	Added old uploaded documents to new repository.	root	5590d 11h	/
84	New directory structure.	root	5590d 11h	/
83	Some fixes from Guy-- replace case with casex.	hharte	5663d 17h	/
82	Clean up spacing	hharte	5673d 13h	/
81	Initial version of TV80 Wishbone Wrapper	hharte	5673d 13h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6773d 02h	/
79	Added JR self-checking test	ghutchis	6773d 02h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6816d 03h	/
77	Added back files lost after server crash	ghutchis	6847d 21h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6927d 03h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6927d 03h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6927d 04h	/
73	Added RC4 encrypt/decrypt test	ghutchis	6938d 23h	/
72	Added copyright header	ghutchis	6938d 23h	/
71	Ported UART from T80	ghutchis	7000d 03h	/
70	Added test for T16450 UART	ghutchis	7050d 22h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7050d 22h	/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7058d 22h	/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7058d 22h	/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7058d 23h	/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7058d 23h	/

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Subversion Repositories tv80

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