URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 65

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
65	Warnings fixed (unused signals removed).	mohor	8267d 04h	/
64	Warnings cleared.	mohor	8267d 04h	/
63	Synplicity was having troubles with the comment.	mohor	8267d 05h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8268d 03h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8268d 21h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8269d 02h	/
59	MSR register fixed.	mohor	8271d 23h	/
58	After reset modem status register MSR should be reset.	mohor	8272d 02h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8273d 02h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8273d 02h	/
55	some synthesis bugs fixed	gorban	8273d 14h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8274d 03h	/
53	Scratch register define added.	mohor	8275d 03h	/
52	Scratch register added	gorban	8275d 16h	/
51	Igor fixed break condition bugs	gorban	8275d 16h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8279d 21h	/
49	committed the debug interface file	gorban	8281d 15h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8282d 14h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8287d 17h	/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8288d 14h	/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8289d 15h	/
44	fixed more typo bugs	gorban	8303d 14h	/
43	lsr1r error fixed.	mohor	8303d 21h	/
42	ti_int_pnd error fixed.	mohor	8303d 21h	/
41	ti_int_d error fixed.	mohor	8303d 21h	/
40	Synthesis bugs fixed. Some other minor changes	gorban	8305d 23h	/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8307d 21h	/
38	small update to test interrupts	gorban	8308d 18h	/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8308d 18h	/
36	no message	mohor	8314d 02h	/

Browse

Tools

Subversion Repositories uart16550

[/] - Rev 65

Filtering Options