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Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8190d 00h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8203d 08h	/
71	Removed confusing comment	gorban	8214d 20h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8220d 05h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8228d 20h	/
68	lsr[7] was not showing overrun errors.	mohor	8232d 03h	/
67	Missing declaration of rf_push_q fixed.	mohor	8239d 03h	/
66	rx push changed to be only one cycle wide.	mohor	8239d 03h	/
65	Warnings fixed (unused signals removed).	mohor	8240d 08h	/
64	Warnings cleared.	mohor	8240d 09h	/
63	Synplicity was having troubles with the comment.	mohor	8240d 09h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8241d 08h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8242d 02h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8242d 06h	/
59	MSR register fixed.	mohor	8245d 03h	/
58	After reset modem status register MSR should be reset.	mohor	8245d 06h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8246d 06h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8246d 06h	/
55	some synthesis bugs fixed	gorban	8246d 18h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8247d 07h	/
53	Scratch register define added.	mohor	8248d 08h	/
52	Scratch register added	gorban	8248d 21h	/
51	Igor fixed break condition bugs	gorban	8248d 21h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8253d 02h	/
49	committed the debug interface file	gorban	8254d 19h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8255d 19h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8260d 21h	/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8261d 18h	/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8262d 19h	/
44	fixed more typo bugs	gorban	8276d 19h	/

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[/] - Rev 73

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