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Subversion Repositories versatile_mem_ctrl

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Rev Log message Author Age Path
48 dq_oe fix unneback 5253d 10h /
47 support for registered outputs on ras, cas and we unneback 5253d 10h /
46 cosmetic updates unneback 5253d 11h /
45 added unneback 5253d 14h /
44 registered row comparison unneback 5255d 13h /
43 unneback 5255d 19h /
42 added pipeline stage for egress FIFO readot unneback 5256d 03h /
41 Added two alternate data capture functions. mikaeljf 5256d 10h /
40 updated fifo interfaces with re/rd and we/wr unneback 5256d 17h /
39 updated FIFO and SDR 16 unneback 5257d 05h /
38 casex in rw state to save logic unneback 5259d 12h /
37 unneback 5260d 03h /
36 unneback 5260d 03h /
35 work for limited test case unneback 5260d 11h /
34 added unneback 5260d 11h /
33 work for limited test case, no cke inhibit for fifo empty unneback 5260d 13h /
32 Updated the testbench to match the new wishbone interface. mikaeljf 5263d 17h /
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5265d 10h /
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5265d 10h /
29 Adapted the test bench to the new wishbone interface. mikaeljf 5269d 10h /
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5269d 12h /
27 unneback 5273d 04h /
26 compiles OK, not simulated unneback 5275d 03h /
25 unneback 5275d 06h /
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5275d 17h /
23 Removed redundant code. mikaeljf 5283d 10h /
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5285d 05h /
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5289d 09h /
20 Minor update of sdc-file. mikaeljf 5291d 10h /
19 Added do-file for Modelsim waveform viewer. mikaeljf 5297d 15h /

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