OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 49

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5287d 23h /
48 dq_oe fix unneback 5287d 23h /
47 support for registered outputs on ras, cas and we unneback 5288d 00h /
46 cosmetic updates unneback 5288d 01h /
45 added unneback 5288d 03h /
44 registered row comparison unneback 5290d 03h /
43 unneback 5290d 08h /
42 added pipeline stage for egress FIFO readot unneback 5290d 16h /
41 Added two alternate data capture functions. mikaeljf 5291d 00h /
40 updated fifo interfaces with re/rd and we/wr unneback 5291d 07h /
39 updated FIFO and SDR 16 unneback 5291d 18h /
38 casex in rw state to save logic unneback 5294d 02h /
37 unneback 5294d 16h /
36 unneback 5294d 17h /
35 work for limited test case unneback 5295d 00h /
34 added unneback 5295d 00h /
33 work for limited test case, no cke inhibit for fifo empty unneback 5295d 03h /
32 Updated the testbench to match the new wishbone interface. mikaeljf 5298d 07h /
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 00h /
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 00h /
29 Adapted the test bench to the new wishbone interface. mikaeljf 5304d 00h /
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5304d 02h /
27 unneback 5307d 17h /
26 compiles OK, not simulated unneback 5309d 16h /
25 unneback 5309d 19h /
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5310d 06h /
23 Removed redundant code. mikaeljf 5317d 23h /
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5319d 19h /
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5323d 22h /
20 Minor update of sdc-file. mikaeljf 5326d 00h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.