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Rev Log message Author Age Path
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8151d 16h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8159d 18h /
35 no message rherveille 8159d 21h /
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8183d 07h /
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8183d 12h /
32 Fixed dat_o incomplete sensitivity list. rherveille 8190d 16h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8199d 12h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8208d 17h /
29 Added wb_ack delay section to testbench rherveille 8208d 17h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8218d 19h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8218d 19h /
26 Added 32bpp tests rherveille 8218d 19h /
25 C-include file.
Initial release		 rherveille 8285d 13h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8292d 16h /
23 Added Copyright/Licence header rherveille 8293d 11h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8313d 08h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8313d 08h /
20 Switched parameter order. rherveille 8322d 12h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8322d 13h /
18 Removed files. They are not used anymore. rherveille 8351d 11h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8351d 11h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8378d 17h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8414d 07h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8415d 02h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8415d 14h /
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8424d 18h /
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8424d 18h /
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8431d 09h /
9 no message rherveille 8432d 03h /
8 Revised core. Removed unused signals rherveille 8437d 11h /

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