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Subversion Repositories vga_lcd

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Rev	Log message	Author	Age	Path
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8173d 17h	/
41	specs version 1.1	rherveille	8173d 17h	/
40	no message	rherveille	8173d 17h	/
39	Changed video timing generator. Changed wishbone master vertical gate count code. Fixed a potential bug in the wishbone slave (cursor color register readout).	rherveille	8173d 18h	/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8173d 18h	/
37	Fixed a potential reset bug in the hint & vint generation.	rherveille	8188d 22h	/
36	Fixed two small bugs that only showed up when the hardware cursors were disabled	rherveille	8196d 23h	/
35	no message	rherveille	8197d 02h	/
34	Added hardware cursor support to wishbone master. Added provision to turn-off 3D cursors. Fixed some minor bugs.	rherveille	8220d 12h	/
33	Added 64x64pixels 4bpp hardware cursor support.	rherveille	8220d 17h	/
32	Fixed dat_o incomplete sensitivity list.	rherveille	8227d 22h	/
31	Some minor bug-fixes. Changed vga_ssel into vga_curproc (cursor processor).	rherveille	8236d 18h	/
30	Fixed some bugs discovered by modified testbench Removed / Changed some strange logic constructions Started work on hardware cursor support (not finished yet) Changed top-level name to vga_enh_top.v	rherveille	8245d 23h	/
29	Added wb_ack delay section to testbench	rherveille	8245d 23h	/
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8256d 00h	/
27	Added 32bpp Fixed some typos Added bandwidth section	rherveille	8256d 01h	/
26	Added 32bpp tests	rherveille	8256d 01h	/
25	C-include file. Initial release	rherveille	8322d 18h	/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8329d 21h	/
23	Added Copyright/Licence header	rherveille	8330d 16h	/
22	VGA Core v2.0 Document revision 0.7	rherveille	8350d 13h	/
21	VGA Core v2.0 Document revision 0.7	rherveille	8350d 13h	/
20	Switched parameter order.	rherveille	8359d 18h	/
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8359d 19h	/
18	Removed files. They are not used anymore.	rherveille	8388d 16h	/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8388d 16h	/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8415d 23h	/
15	Created directory structure (documentation, vhdl, verilog)	rherveille	8451d 12h	/
14	Added CLUT bank switching. Replaced multiplier with simple counters. Fixed timing bug.	rherveille	8452d 07h	/
13	Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore.	rherveille	8452d 20h	/

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