URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 60

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Rev	Log message	Author	Age	Path
60	all WB outputs are registered, but just when we dont use cursors	markom	7568d 05h	/
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7600d 11h	/
58	Enabled Fifo Underrun test	rherveille	7600d 11h	/
57	1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. 2) Changed top level and pixel generator to reflect changes in the fifo. 3) Changed a bug in vga_fifo. 4) Changed pixel generator and wishbone master to reflect changes.	rherveille	7621d 06h	/
56	Removed 'or negedge arst' from sluint/luint sensitivity list	rherveille	7650d 03h	/
55	Initial release.	rherveille	7707d 03h	/
54	Added DVI tests	rherveille	7707d 03h	/
53	Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. Blocks are located more logically now. Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.	rherveille	7707d 08h	/
52	Numerous updates and added checks	rherveille	7707d 08h	/
51	Forgot to change document revision number	rherveille	7755d 03h	/
50	Forgot to change document revision	rherveille	7755d 03h	/
49	Added WISHBONE revB.3 signals	rherveille	7755d 04h	/
48	WISHBONE revB.3 signals added	rherveille	7755d 04h	/
47	Added wb_b3_check Removed ud_cnt, ro_cnt	rherveille	7756d 00h	/
46	Added WISHBONE revB.3 sanity checks	rherveille	7756d 00h	/
45	Changed timing generator; made it smaller and easier.	rherveille	7756d 05h	/
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7756d 06h	/
43	Added WISHBONE revB.3 Registered Feedback Cycles support	rherveille	7756d 20h	/
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8089d 06h	/
41	specs version 1.1	rherveille	8089d 06h	/
40	no message	rherveille	8089d 07h	/
39	Changed video timing generator. Changed wishbone master vertical gate count code. Fixed a potential bug in the wishbone slave (cursor color register readout).	rherveille	8089d 08h	/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8089d 08h	/
37	Fixed a potential reset bug in the hint & vint generation.	rherveille	8104d 11h	/
36	Fixed two small bugs that only showed up when the hardware cursors were disabled	rherveille	8112d 13h	/
35	no message	rherveille	8112d 16h	/
34	Added hardware cursor support to wishbone master. Added provision to turn-off 3D cursors. Fixed some minor bugs.	rherveille	8136d 02h	/
33	Added 64x64pixels 4bpp hardware cursor support.	rherveille	8136d 07h	/
32	Fixed dat_o incomplete sensitivity list.	rherveille	8143d 12h	/
31	Some minor bug-fixes. Changed vga_ssel into vga_curproc (cursor processor).	rherveille	8152d 07h	/

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Subversion Repositories vga_lcd

[/] - Rev 60

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