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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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Rev Log message Author Age Path
45 Fixed duplicate driver and Vivado 2018.1 PCIe core fransschreuder 1884d 12h /
44 EDITED: added image size aborga 1972d 04h /
43 ADDED: README.md to be parsed by the OC project page aborga 1972d 09h /
42 Added filter in wuppercodegen in order to generate 2d arrays of registers fransschreuder 2317d 09h /
41 Added brief description of Wishbone broel 2417d 09h /
40 Updated comment header for syscon. broel 2417d 10h /
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2421d 05h /
38 Fixed include of stdint.h broel 2429d 12h /
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen		 fransschreuder 2430d 04h /
36 Updated documentation fransschreuder 2765d 05h /
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2819d 10h /
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 2925d 05h /
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 2970d 04h /
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2970d 04h /
31 Added example application documentation. oussamak 3064d 05h /
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3064d 06h /
29 Improved application to reflect both up and down transfers fransschreuder 3106d 04h /
28 Added registermap reset fransschreuder 3106d 06h /
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3106d 09h /
26 Added sys_clk constraint fransschreuder 3106d 11h /
25 Added scripts and constraints for KCU105 fransschreuder 3106d 11h /
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3107d 05h /
23 Fixed reset of application registers fransschreuder 3164d 10h /
22 Added dma_soft_reset to trigger register resets fransschreuder 3170d 10h /
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3179d 07h /
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3193d 06h /
19 * driver/README updated oussamak 3199d 08h /
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3199d 10h /
17 Changed name of toplevel, to make tree consistent oussamak 3213d 12h /
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3263d 06h /

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