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Rev Log message Author Age Path
33 Update with some new pin information rehayes 5385d 23h /
32 added ram block rehayes 5385d 23h /
31 Cleanup for MAX_CHANNEL bus rehayes 5397d 18h /
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5397d 18h /
29 Added some constant assigments, still needs more work to complete rehayes 5397d 18h /
28 Added comment line rehayes 5397d 18h /
27 Subversion test, no actual code changes rehayes 5410d 17h /
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5412d 20h /
25 Fix connected net name rehayes 5412d 20h /
24 Delete unused inputs rehayes 5412d 21h /
23 Oct 7, 2009 Update rehayes 5418d 18h /
22 Updated with figures and some new features rehayes 5418d 18h /
21 Added timeout, total error count, and XGCHN test rehayes 5418d 18h /
20 Added event signal for compare error tracking in top level test bench. rehayes 5418d 18h /
19 Verilog memory image for testing rehayes 5418d 18h /
18 Complete XGCHN test code rehayes 5418d 18h /
17 Additions for XGCHID debug commands rehayes 5418d 18h /
16 Copy of what was in the bench directory rehayes 5418d 19h /
15 Fix R1 load at boot up, add debug features rehayes 5431d 16h /
14 Sept 23 2009 Change update rehayes 5432d 19h /
13 Debug functions test code rehayes 5432d 19h /
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5432d 19h /
11 Update with Single Step debuging test rehayes 5432d 19h /
10 Minor Cleanup rehayes 5437d 19h /
9 Update for new testbench usage rehayes 5438d 17h /
8 Clean up, Fix default ISR rehayes 5438d 17h /
7 Fix to take advantage of change to sconv program. rehayes 5444d 16h /
6 Update to create output file name from input file name by changing extension to .v rehayes 5444d 16h /
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5445d 19h /
4 Clean up rehayes 5453d 16h /

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