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Subversion Repositories xgate

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Rev	Log message	Author	Age	Path
62	Cleanup implicit wire declarations.	rehayes	5204d 11h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5211d 11h	/
60	Add ability at insert wait states on RAM access	rehayes	5211d 11h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5211d 11h	/
58	WISHBONE Bus update.	rehayes	5263d 11h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5263d 14h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5279d 15h	/
55	Minor change to instruction set details.	rehayes	5279d 15h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5279d 15h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5279d 15h	/
52	Minor changes to aide waveform debug	rehayes	5279d 15h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5295d 11h	/
50	incremental update to match status bit changes	rehayes	5295d 11h	/
49	First pass with instruction set details	rehayes	5295d 12h	/
48	Update for SBC ana ADC condition code changes	rehayes	5295d 12h	/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5295d 12h	/
46	Update to remove stack registers and add new register text.	rehayes	5327d 10h	/
45	Update to remove stack registers and add new register text.	rehayes	5327d 10h	/
44	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5329d 09h	/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5329d 09h	/
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5329d 09h	/
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5330d 11h	/
40	Update for single program counter adder	rehayes	5350d 14h	/
39	delete	rehayes	5358d 15h	/
38	Nov 9 2009 update notes	rehayes	5358d 16h	/
37	RAM model breakout for testbench	rehayes	5358d 16h	/
36	Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls.	rehayes	5358d 16h	/
35	Add byte lane select input to all tasks	rehayes	5358d 16h	/
34	minor changes related to wishbone master interface	rehayes	5358d 16h	/
33	Update with some new pin information	rehayes	5358d 16h	/

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Subversion Repositories xgate

[/] - Rev 62

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