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Rev	Log message	Author	Age	Path
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5158d 05h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5159d 07h	/
70	Updated with interrupt bypass controll registers.	rehayes	5159d 07h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5159d 08h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5159d 08h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5159d 08h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5179d 04h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5179d 04h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5179d 04h	/
63	Remove historical output ports that are no longer used.	rehayes	5189d 04h	/
62	Cleanup implicit wire declarations.	rehayes	5189d 04h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5196d 03h	/
60	Add ability at insert wait states on RAM access	rehayes	5196d 03h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5196d 03h	/
58	WISHBONE Bus update.	rehayes	5248d 03h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5248d 06h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5264d 07h	/
55	Minor change to instruction set details.	rehayes	5264d 07h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5264d 07h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5264d 07h	/
52	Minor changes to aide waveform debug	rehayes	5264d 07h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5280d 03h	/
50	incremental update to match status bit changes	rehayes	5280d 03h	/
49	First pass with instruction set details	rehayes	5280d 04h	/
48	Update for SBC ana ADC condition code changes	rehayes	5280d 04h	/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5280d 04h	/
46	Update to remove stack registers and add new register text.	rehayes	5312d 02h	/
45	Update to remove stack registers and add new register text.	rehayes	5312d 02h	/
44	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5314d 01h	/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5314d 01h	/

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Subversion Repositories xgate

[/] - Rev 72

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