URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 76

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Rev	Log message	Author	Age	Path
76	Updated xgate_risc.v for xlink synthesis warnings.	rehayes	5220d 08h	/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5220d 09h	/
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5225d 10h	/
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5225d 10h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5225d 10h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5226d 12h	/
70	Updated with interrupt bypass controll registers.	rehayes	5226d 12h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5226d 13h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5226d 13h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5226d 13h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5246d 09h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5246d 09h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5246d 09h	/
63	Remove historical output ports that are no longer used.	rehayes	5256d 08h	/
62	Cleanup implicit wire declarations.	rehayes	5256d 08h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5263d 08h	/
60	Add ability at insert wait states on RAM access	rehayes	5263d 08h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5263d 08h	/
58	WISHBONE Bus update.	rehayes	5315d 08h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5315d 11h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5331d 12h	/
55	Minor change to instruction set details.	rehayes	5331d 12h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5331d 12h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5331d 12h	/
52	Minor changes to aide waveform debug	rehayes	5331d 12h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5347d 08h	/
50	incremental update to match status bit changes	rehayes	5347d 08h	/
49	First pass with instruction set details	rehayes	5347d 09h	/
48	Update for SBC ana ADC condition code changes	rehayes	5347d 09h	/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5347d 09h	/

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[/] - Rev 76

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