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Subversion Repositories xgate

[/] - Rev 91

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Rev	Log message	Author	Age	Path
91	Update to use one ISR to handle all 127 interrupts.	rehayes	4571d 20h	/
90	Cosmetic omment changes.	rehayes	4571d 20h	/
89	Code cleanup.	rehayes	4585d 19h	/
88	Updated with complete code	rehayes	4659d 04h	/
87	First pass JTAG TAP, state machine working but needs work to complete reset of TAP.	rehayes	4785d 18h	/
86	Add JTAG test tasks	rehayes	4785d 18h	/
85	Corrections to instruction set details example code, added test bench debugger.	rehayes	5060d 03h	/
84	Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections.	rehayes	5060d 03h	/
83	Add subroutine quailifier.	rehayes	5060d 03h	/
82	Added debug module to assist in software debugging.	rehayes	5060d 22h	/
81	Initial checkin of the SKIPJACK encrypt/decrypt application program	rehayes	5060d 22h	/
80	Added IRQ bypass registers and Test bench appendix	rehayes	5122d 23h	/
79	Added IRQ bypass registers and Test bench appendix	rehayes	5122d 23h	/
78	Added IRQ bypass registers and Test bench appendix	rehayes	5122d 23h	/
77	Documentation update	rehayes	5122d 23h	/
76	Updated xgate_risc.v for xlink synthesis warnings.	rehayes	5146d 00h	/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5146d 00h	/
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5151d 01h	/
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5151d 01h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5151d 01h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5152d 04h	/
70	Updated with interrupt bypass controll registers.	rehayes	5152d 04h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5152d 04h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5152d 05h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5152d 05h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5172d 00h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5172d 00h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5172d 00h	/
63	Remove historical output ports that are no longer used.	rehayes	5182d 00h	/
62	Cleanup implicit wire declarations.	rehayes	5182d 00h	/

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[/] - Rev 91

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